1. Technical Field
The invention relates generally to digital to analogue converters (DAC), and more specifically, to the design of a Gray Code to Thermometer Code decoder circuit for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations.
2. Related Art
High performance SRAMs produced in conformity with the DDR3 specification are required to incorporate on-chip programmable termination at all input pads. The value of digitally adjustable termination resistors are typically programmed to match a multiple of the line impedance, Z0, to improve signal integrity in the interface between two chips. Digitally adjustable resistors are digital-to-analog converters (DACs).
Programable Termination Circuitry
A programmable terminator circuit can be constructed from binary weighted devices presenting a tunable impedance at each chip pad. For instance, a 4 bit binary weighted termination circuit has 4 devices of widths 1xc3x97, 2xc3x97, 4xc3x97, 8xc3x97, for a total width of 15xc3x97. The gate inputs to theses devices are driven by the latched outputs of a 4 bit binary code counter. This design has the disadvantage of possibly changing multiple bits as the count is incremented or decremented by one. For example, if the 4-bit count is incremented from 7 to 8, the binary count changes from 0111 to 1000; all four bits change. If timing skews or noise is present, it is possible to see a count of 0000 (max. impedance), or 1111 (min. impedance), or various other combinations while the bits are changing from 7 to 8. If the skew/noise is moderate, these transient counts appear as impedance glitches on the interface which can reduce signal integrity. If the skew/noise is more severe, it is possible to get an xe2x80x98impartial count updatexe2x80x99 if the incorrect state of any bit is latched into downstream registers.
Using Gray code counting (in conjunction with Unary/Thermometer code decodingxe2x80x94discussed below) avoids the problem discussed above of simultaneously changing multiple bits since only one bit changes as the count is incremented or decremented by one. For instance, changing the count from 7 to 8, results in the equivalent Gray code count changing from 0100 to 1100; only one bit (the MSB) changes. Even if severe skew/noise is present, the contents of downstream latches will either remain 0100 or get updated to 1100.
Equally weighted termination devices can be used in place of binary weighted device sizes. An equally weighted termination circuit has 15 devices of 1xc3x97 width and a total width of 15xc3x97. The equally weighted termination circuit however requires that the 4 bit Gray code count be decoded into a 15-bit unary code count (e.g., a redundant Thermometer code wherein, e.g., 10010101101101 equals 001110101101010). A thermometer-coded scheme can be improved by using resistive device-shape factors that produce incremental changes in conductance that are a fixed percentage of accumulated conductance. This idea leads to a slowly tapering set of sizes in the resistor elements. See generally, Digital Systems Engineering, Dally (Cambridge U. Press 1999) section 11.1.3.2.
Table 1 is a logic table illustrating how a 4-Bit Gray code to 15-Bit Thermometer code Decoder would operate in logical theory, wherein all Thermometer code outputs 1-15 are active-high (i.e., a High voltage indicated symbolically by a xe2x80x9c1xe2x80x9d characterizes the xe2x80x9cactivexe2x80x9d state of the active-high output).
FIG. 2 illustrates the manner in which a real 4-Bit Gray code to 15-Bit Thermometer code Decoder would operate in real time while monotonically incrementing from Thermometer code count 0 to count 15. The Gray code count is sequentially incremented from count zero to count 15 via bits A, B, C, and D which results in the Thermometer code count incrementing from count zero to count 15 via bits 1-15.
An advantage of the Gray code to Thermometer code system is that the magnitude of any potential impedance glitch is further reduced, since when the impedance count is updated (e.g., incremented or decremented by a single unit), a single device of width=1xc3x97 is either enabled (counting up) or disabled (counting down). This corresponds to a relatively small change in the total value of the termination impedance and produces a smaller glitch on the interface than that produced when multiple devices are switched (as may occur in a binary weighted system). Also, the potential for a relatively large change in terminator impedance due to an xe2x80x9cimpartial count updatexe2x80x9d is eliminated.
FIG. 3 depicts a topology of a simple Combinational Logic Decoder 100 that utilizes Combinational logic circuits to convert Gray code into Thermometer code (FIG. 3). This topology includes one cell per output bit, each cell being adapted to be activated by a particular count of the gray code or any higher count. For example, 15 cells would correspond to the 15 output bits of Thermometer code, and upon the occurrence of count 15, all 15 cells would be active. Each cell contains different Combinational logic circuitry (e.g., a different selection or arrangement of Combinational logic gates) corresponding to the specific input/output relationship of each cell. The output of each cell depends solely on the Gray coded inputs and is independent of the outputs of other cells. To output the desired Thermometer code, the corresponding Gray code is inputted without any reset. To set the Thermometer code to a different value, the new Gray code is inputted without any reset command. The Combinational cells have no memory or feedback mechanisms. The past output values have no bearing on current output values. Thus, if the Gray code input value changes by more than one (e.g., from a Gray coded 1 to a Gray coded 4,) the Thermometer code output will change by more than one (e.g., by 3).
FIGS. 4, 5 and 6 each show the combinational (i.e., combinatorial) logic within one the cells depicted in FIG. 3. The output of these cells directly corresponds to the above Thermometer code in Table 1.
FIG. 4 depicts exemplary combinational logic gates within CELL1 of the simple Combinational Logic Decoder 100 of FIG. 3. CELL1 can be implemented with a NAND gate (1NAND) composed of 8 CMOS (Complementary Metal Oxide Semiconductor) transistors (i.e, the device count in CELL1 is 8).
FIG. 5 depicts exemplary combinational logic gates within CELL3 of the simple Combinational Logic Decoder 100 of FIG. 3. CELL3 can be implemented with two (cascaded) NAND gates (3NAND1 and 3NAND2) composed of 10 CMOS transistors (i.e, the device count in CELL3 is 10).
FIG. 6 depicts exemplary combinational logic gates within CELL13 of the simple Combinational Logic Decoder 100 of FIG. 3. CELL13 can be implemented with three (cascaded) gates (13NAND1, 13NOR1, 13NOR2) composed of 12 CMOS transistors.
The disclosed Area Efficient Sequential Decoder (AESD) topology (illustrated by the exemplary 4-Gray-code-bit decoder 200 in FIG. 8a) overcomes the limitations of a combinational logic decoder (e.g., decoder 100 of FIG. 3) for decoding a gray coded count into a unary coded count (e.g., thermometer coded count). The disclosed AESD topology (see FIG. 8a) provides a lower device count when compared to the simple combinational logic solution 100. For example, for a 4 Gray code bit to 15 Thermometer code bit decoder, the AESD topology (200) uses only 90 (or fewer, see optimization methods discussed below) devices. The simple Combinational logic solution (See FIGS. 3, 4, 5, and 6) uses a practical minimum of 124 devices. As the number of Gray coded bits to be decoded increases (i.e., as the order N of the decoder increases), the AESD topology continues to outperform the simple Combinational logic solution in device count. Although the exemplary AESD decoder 200 decodes a 4-bit Gray coded word, the AESD topology is Area Efficient for and capable of decoding sequences of N-bit Gray code words, where N is any integer number equal to or greater than 1. A single AESD decoder may be employed to control a plurality of termination devices (e.g., wired in parallel).
FIG. 7 shows the relationship between the number of Gray coded bits to be decoded, and the numbers of devices needed for decoding Gray code into Thermometer code using the topology of Combinational logic decoder 100 (of FIG. 3) and the disclosed topology of a sequential decoder (e.g., decoder 200 of FIG. 8a).
The minimization of devices needed to implement a Gray code to Thermometer code decoder allows the AESD topology decoder to be area efficient. Each cell of the decoder and an entire AESD decoder 200 may be implemented as an integrated circuit on a chip (e.g., chip 10 shown in FIG. 1). One or more copies of the AESD decoder may be provided to each signal line pad on the chip to control termination at each pad. (E.g., two decoders 200 may be used at each of K (clock, address, data and control) pads of an integrated circuit chip 10, e.g., for implementing each of 2K decoders on the chip 10 of FIG. 1). Thus, the area efficiency of the AESD decoder becomes more significant as the number of pads to be terminated increases.
Another feature of the AESD topology is that no more than two unique decoder cell topologies (see, e.g., FIGS. 9 and 10) are needed to implement the area efficient decoder. (In an alternative embodiment of the invention depicted in FIG. 12, a single self-cascading cell topology is used to implement all the cells of a sequential decoder, each self-cascading cell having an increased device-count).
A feature that further distinguishes the Sequential (AESD) Decoder 200 from the Combinational decoder 100 is that the operation of the AESD decoder relies upon sequential counting (up or down in order) of the inputted Gray code count, and thus provides incremental changes in the Thermometer coded output. In other words, the Thermometer coded count that is asserted by the decoder will be incremented or decremented one count at a time. This feature supports fixed percentage increases of accumulated conductance, and helps to avoid noise which can arise from rapid multi-count changes of the programmed termination impedance values.
Accordingly, a first aspect of the invention provides a circuit for decoding an N-bit (e.g., 4-bit) gray coded count into a count of a unary code (e.g., Thermometer code), comprising: a first cell having a first input and a first output; a second cell having a second input and a second output; a third cell having a third input and a third output, wherein the first output is gated by feedback from the second output, the second output is gated by feedforward from the first output and by feedback from the third output, and the third outputted is gated by feedforward from the second output, wherein the first, second and third inputs are each selected from gray code bits of the gray coded count and the logical complements of said gray code bits, and wherein the first, second and third outputs are each a different bit of the unary coded count or the logical complement of such a bit.
A second aspect of the invention provides an apparatus for decoding a consecutive sequence of N-bit Gray coded words, comprising: a sequential Gray code to Thermometer code decoder.
A third aspect of the invention provides a Gray code decoder comprising: a plurality of cascaded decoding-latching stages, each decoding-latching stage responsive to an individual one of single-bit changes between consecutive counts in a Gray code, each decoding-latching stage adapted to detecting and latching the occurrence of one such single-bit change, each decoding and latching stage having a decoding-latching circuit. In some embodiments, decoding-latching circuits having inverted outputs which can be serially alternating with decoding-latching circuits having noninverted outputs.
A fourth aspect of the invention provides a circuit for decoding counts of an N-bit gray code to up to 2Nxe2x88x921 Thermometer coded bits, comprising: a plurality (u) of cells, each cell being adapted to output a single bit of the Thermometer coded bits, wherein an output of each of the u cells is influenced by an operative connection from an output of any next cell and is further influenced by an operative connection from an output of any prior cell.
A fifth aspect of the invention provides an apparatus for converting gray code to thermometer code, the apparatus comprising: a plurality of modules, each module receiving one bit of the gray code and outputting a bit of the thermometer code, each module being coupled serially to another module.
A sixth aspect of the invention provides a method for decoding a consecutive sequence of N-bit Gray coded words, comprising: sequentially decoding Gray code to Thermometer code.
A seventh aspect of the invention provides a method of Gray code decoding, comprising: providing a plurality of cascaded decoding-latching stages, each decoding-latching stage responsive to an individual one of single-bit changes between consecutive counts in a Gray code, each decoding and latching stage having a decoding-latching circuit; and detecting and latching, by each decoding-latching stage, the occurrence of each such single-bit change.
A eighth aspect of the invention provides a method for decoding counts of an N-bit gray code to up to u Thermometer coded bits, comprising: providing a plurality (u) of cells, wherein u is an integer equal to or less than 2Nxe2x88x921; and outputting by each cell a single bit of the Thermometer coded bits, wherein the outputting by each said cell is influenced by an operative connection from an output of any next cell and is further influenced by an operative connection from an output of any prior cell.
A ninth aspect of the invention provides a method for converting gray code to thermometer code, the method comprising: providing a plurality of modules; coupling each module serially to another module; receiving by each module one bit of the gray code; and outputting by each module a bit of the thermometer code.